PC912XDP512F0MPVR datasheet(1002/1348 Pages) FREESCALE

1002 / 1348 page

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1004

Freescale Semiconductor

Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status

bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be

used as general purpose I/O.

Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and

1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and

0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with

the SCI, these pins can be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

24.0.5.20 Port S Input Register (PTIS)

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This also can be used to detect

overload or short circuit conditions on output pins.

24.0.5.21 Port S Data Direction Register (DDRS)

Read: Anytime.

Write: Anytime.

This register configures each port S pin as either input or output.

If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.

76543210

PTIS7

PTIS6

PTIS5

PTIS4

PTIS3

PTIS2

PTIS1

PTIS0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

————————

= Unimplemented or Reserved

Figure 24-22. Port S Input Register (PTIS)

76543210

DDRS7

DDRS6

DDRS5

DDRS4

DDRS3

DDRS2

DDRS1

DDRS0

Reset

00000000

Figure 24-23. Port S Data Direction Register (DDRS)

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