PC912XDP512F0MPVR datasheet(1014/1348 Pages) FREESCALE

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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1016

Freescale Semiconductor

24.0.5.42 Port H Data Register (PTH)

Read: Anytime.

Write: Anytime.

Port H pins 7–0 are associated with the routed SPI1.

These pins can be used as general purpose I/O when not used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is

enabled. Refer to SPI section for details.

24.0.5.43 Port H Input Register (PTIH)

Read: Anytime.

Write: Never, writes to this register have no effect.

Table 24-40. PIFP Field Descriptions

Field

Description

7–0

PIFP[7:0]

Interrupt Flags Port P

0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.

76543210

PTH7

PTH6

PTH5

PTH4

PTH3

PTH2

PTH1

PTH0

Routed

SPI

SS1

SCK1

MOSI1

MISO1

Reset

00000000

Figure 24-44. Port H Data Register (PTH)

76543210

PTIH7

PTIH6

PTIH5

PTIH4

PTIH3

PTIH2

PTIH1

PTIH0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

————————

= Unimplemented or Reserved

Figure 24-45. Port H Input Register (PTIH)

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