PC912XDP512F0MPVR datasheet(1010/1348 Pages) FREESCALE

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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1012

Freescale Semiconductor

24.0.5.34 Port P Data Register (PTP)

Read: Anytime.

Write: Anytime.

Port P pins 7–0 are associated with the PWM as well as the SPI1. These pins can be used as general

purpose I/O when not used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

The PWM function takes precedence over the general purpose I/O and the SPI1 function if the associated

PWM channel is enabled. While channels 6-0 are output only if the respective channel is enabled, channel

7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section for details.

The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section

for details.

24.0.5.35 Port P Input Register (PTIP)

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to detect

overload or short circuit conditions on output pins.

76543210

PTP7

PTP6

PTP5

PTP4

PTP3

PTP2

PTP1

PTP0

PWM

PWM7

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

SPI

SS1

SCK1

MOSI1

MISO1

Reset

00000000

Figure 24-36. Port P Data Register (PTP)

76543210

PTIP7

PTIP6

PTIP5

PTIP4

PTIP3

PTIP2

PTIP1

PTIP0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

————————

= Unimplemented or Reserved

Figure 24-37. Port P Input Register (PTIP)

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