PC912XDP512F0MPVR datasheet(1049/1348 Pages) FREESCALE

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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1051

All EDHI and EDLO bits are readable and writable in special modes.

25.4

Functional Description

25.4.1

EEPROM Command Operations

Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify

algorithms described in this section. The program, erase, and sector modify algorithms are controlled by

a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider.

The command register as well as the associated address and data registers operate as a buffer and a register

(2-stage FIFO) so that a second command along with the necessary data and address can be stored to the

buffer while the ﬁrst command is still in progress. Buffer empty as well as command completion are

signalled by ﬂags in the EEPROM status register with interrupts generated, if enabled.

The next sections describe:

1. How to write the ECLKDIV register

2. Command write sequences to program, erase, erase verify, sector erase abort, and sector modify

operations on the EEPROM memory

3. Valid EEPROM commands

4. Effects resulting from illegal EEPROM command write sequences or aborting EEPROM

operations

25.4.1.1

Writing the ECLKDIV Register

Prior to issuing any EEPROM command after a reset, the user is required to write the ECLKDIV register

to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase

timings are also a function of the bus clock, the ECLKDIV determination must take this information into

account.

If we deﬁne:

•

ECLK as the clock of the EEPROM timing control block

•

Tbus as the period of the bus clock

•

INT(x) as taking the integer part of x (e.g., INT(4.323)=4)

then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 25-17.

For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz,

ECLKDIV bits EDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting EECLK

frequency is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased

over the optimum target by:

If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits

EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is

200 190

–

() 200

⁄

100

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