ADS58C48IPFPR datasheet(41/70 Pages) TI

41 / 70 page

79.5

80.5

81.5

82.5

66.5

66.6

66.7

66.8

66.9

67.1

67.2

67.3

THD

Input Clock Duty Cycle (%)

SNR

Fin = 20MHz

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

100

120

140

160

180

200

Sampling Frequency (MSPS)

AVDD = 1.8V

Fin = 2.5MHz

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

100

120

140

160

180

200

Sampling Frequency (MSPS)

Default after Reset

Digital Gain + Offset-Correction Enable

SNR Boost ON for 2ch’s (60MHz Filter)

SNR Boost ON for 4ch’s (60MHz Filter)

SNR Boost ON for 4ch’s + Digital Gain

+ Offset Correction

ADS58C48

www.ti.com

SLAS689 – MAY 2010

TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP

differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,

DDR LVDS output interface, 32k point FFT (unless otherwise noted)

PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE

Figure 40.

ANALOG POWER

DIGITAL POWER

SAMPLING FREQUENCY

Figure 41.

Figure 42.

Submit Documentation Feedback

Product Folder Link(s) :ADS58C48

ADS58C48IPFPR 데이터시트(PDF) 41 Page - Texas Instruments

ADS58C48IPFPR 데이터시트(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

데이터시트 다운로드

링크 URL