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ADS58C48IPFPR 데이터시트(PDF) 15 Page - Texas Instruments

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부품명 ADS58C48IPFPR
상세설명  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

ADS58C48IPFPR 데이터시트(HTML) 15 Page - Texas Instruments

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T0108-01
t
1
t
3
t
2
PowerSupply
AVDD,DRVDD
RESET
SEN
ADS58C48
www.ti.com
SLAS689 – MAY 2010
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
1
ms
t2
Reset pulse width
Pulse width of active RESET signal
10
ns
1
µs
t3
Register write delay
Delay from RESET disable to SEN active
100
ns
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
Figure 8. Reset Timing Diagram
Copyright © 2010, Texas Instruments Incorporated
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