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ADS58C48IPFPR 데이터시트(PDF) 22 Page - Texas Instruments

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부품명 ADS58C48IPFPR
상세설명  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

ADS58C48IPFPR 데이터시트(HTML) 22 Page - Texas Instruments

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ADS58C48
SLAS689 – MAY 2010
www.ti.com
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
41
00
<LVDS CMOS>
<CMOS CLKOUT
0
0
<PDN OBUF LVDS>
STRENGTH>
D7-D6
<LVDS CMOS>
00
LVDS interface
01
CMOS interface
10
CMOS interface
11
CMOS interface
D5-D4
<CMOS CLKOUT STRENGTH>
00
Maximum strength (recommended and used for specified timings)
01
Medium strength
10
Low strength
11
Very low strength
D1-D0
<PDN OBUF LVDS>
00
LVDS data buffers enabled for all channels
01
LVDS data buffers powered down and output 3-stated for channel A and channel D
10
LVDS data buffers powered down and output 3-stated for channel B and channel C
11
LVDS data buffers powered down and output 3-stated for all channels including the LVDS output
clock buffer
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
42
00
<CLKOUT FALL POSN>
<CLKOUT RISE
<DIGITAL
<PDN OBUF CMOS>
0
POSN>
MODE 1>
D7-D6
<CLKOUT FALL POSN>
00
Default position (timings are specified in this condition)
01
Setup increases by 450 ps, hold decreases by 450 ps
10
Setup decreases by 300 ps, Hold increases by 300 ps
In this setting, the bit order is swapped compared to default case.
For example, default order is [CLKOUTP fall-D1, CLKOUTP rise –D2]. In this setting, the order
becomes [CLKOUTP fall-D2, CLKOUTP rise –D1]
11
Setup increases by 1.0 ns, Hold decreases by 1.0 ns
D5-D4
<CLKOUT RISE POSN>
00
Default position (timings are specified in this condition)
01
Setup increases by 550 ps, hold decreases by 550 ps
10
Setup increases by 600 ps, Hold decreases by 600 ps
In this setting, the bit order is swapped compared to default case.
For example, default order is [CLKOUTP fall-D1, CLKOUTP rise –D2] In this setting, the order
becomes [CLKOUTP fall-D2, CLKOUTP rise –D1]
11
Setup increases by 1.1 ns, Hold decreases by 1.1 ns
22
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :ADS58C48



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