f − Frequency − MHz

0

10

20

30

40

50

60

70

80

90

100

5

10

15

20

25

30

35

40

45

50

55

G005

21 W

ESR = 60

ESR = 50

ESR = 40

ESR = 30

ESR = 25

ESR = 15

XO

or

2LVCMOS

or

Differential

Input

CLK_IN0

CLK_IN1

CLK_SEL

(1)

InputSourceSelect

(FromEEPROM)

S0378-01

CDCE706

Figure 15. Crystal Drive Power

For example, if a 27-MHz crystal with ESR of 50

level should be held to a minimum to avoid overdriving the crystal. The maximum power dissipation is specified

for each type of crystal in the oscillator specifications, i.e., 100

µW for the example above.

Single-Ended LVCMOS Clock Inputs

When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock input pins and can be

driven up to 200 MHz. Both clock input circuits are equal in design and can be used independently of each other

(see Figure 16). The internal clock select bit, byte 10, bit [4], selects one of the two input clocks. CLK_IN0 is the

default selection. There is also the option to program the external control pin S0/A0/CLK_SEL as the clock-select

pin, byte 10, bits [1:0].

The two clock inputs can be used for redundancy switching, i.e., to switch between a primary clock and

secondary clock. Note that a phase difference between the clock inputs may require PLL correction. Also, in case

of different frequencies between the primary and secondary clock, the PLL must re-lock to the new frequency.

(1)

CLK_SEL is optional and can be configured by EEPROM setting.

Figure 16. LVCMOS Clock Input Circuitry

Copyright © 2005–2008, Texas Instruments Incorporated

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