CDCE706 datasheet(32/40 Pages) TI

32 / 40 page

Cycle

−40

−30

−20

−10

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

G008

Cycle

−25

−20

−15

−10

−5

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

G009

CDCE706

SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com

Figure 26. Snapshot of Cycle-to-Cycle Jitter

Period jitter (tjit(per)) is the deviation in cycle time of a clock signal with respect to the ideal period (1/fO) over a

random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal that

would ever occur on the PLL outputs. This is also referred to as short-term jitter.

Figure 27. Snapshot of Period Jitter

Phase jitter (tjit(phase)) is the long-term variation of the clock signal. It is the cumulative deviation in t(Θ) for a

controlled edge with respect to a t(

Θ) mean in a random sample of cycles. Phase jitter, time-interval error (TIE),

and wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is

defined as phase variation at rates less than 10 Hz, whereas jitter is defined as phase variation greater than

10 Hz. The measurement interval must be long enough to gain a meaningful result. Wander can be caused by

temperature drift, aging, supply-voltage drift, etc.

Submit Documentation Feedback

Product Folder Link(s): CDCE706

CDCE706 데이터시트(PDF) 32 Page - Texas Instruments

CDCE706 데이터시트(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

데이터시트 다운로드

링크 URL