XIO2001IPNP datasheet(109/131 Pages) TI

109 / 131 page

XIO2001

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SCPS212D – MAY 2009 – REVISED JANUARY 2010

Table 6-7. Serial IRQ Edge Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

IRQ 15 edge mode

15(1)

IRQ15_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 14 edge mode

14(1)

IRQ14_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 13 edge mode

13(1)

IRQ13_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 12 edge mode

12(1)

IRQ12_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 11 edge mode

11(1)

IRQ11_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 10 edge mode

10(1)

IRQ10_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 9 edge mode

9(1)

IRQ9_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 8 edge mode

8(1)

IRQ8_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 7 edge mode

7(1)

IRQ7_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 6 edge mode

6(1)

IRQ6_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 5 edge mode

5(1)

IRQ5_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 4 edge mode

4(1)

IRQ4_MODE

0 = Edge mode (default)

1 = Level mode

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Memory-Mapped TI Proprietary Register Space

109

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