EPCS4 datasheet(14/38 Pages) ALTERA

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Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

Serial Configuration Device Memory Access

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

Operation Codes

This section describes the operations that can be used to access the memory in serial

configuration devices. The DATA, DCLK, ASDI, and nCS signals access the memory in

serial configuration devices. All serial configuration device operation codes,

addresses and data are shifted in and out of the device serially, with the most

significant bit (MSB) first.

The device samples the active serial data input on the first rising edge of the DCLK

after the active low chip select (nCS) input signal is driven low. Shift the operation

code (MSB first) serially into the serial configuration device through the active serial

data input (ASDI) pin. Each operation code bit is latched into the serial configuration

device on the rising edge of the DCLK.

Different operations require a different sequence of inputs. While executing an

operation, you must shift in the desired operation code, followed by the address

bytes, data bytes, both, or neither. The device must drive nCS high after the last bit of

the operation sequence is shifted in. Table 3–8 lists the operation sequence for every

operation supported by the serial configuration devices.

For the read byte, read status, and read silicon ID operations, the shifted-in operation

sequence is followed by data shifted out on the DATA pin. You can drive the nCS pin

high after any bit of the data-out sequence is shifted out.

For the write byte, erase bulk, erase sector, write enable, write disable, and write

status operations, drive the nCS pin high exactly at a byte boundary (drive the nCS

pin high a multiple of eight clock pulses after the nCS pin is driven low); otherwise,

the operation is rejected and is not executed.

All attempts to access the memory contents while a write or erase cycle is in progress

will not be granted, and the write or erase cycle will continue unaffected.

H'10000

H'1FFFF

H'00000

H'0FFFF

Table 3–7. Address Range for Sectors in EPCS1

Sector

Address Range (Byte Addresses in HEX)

Start

End

H'18000

H'1FFFF

H'10000

H'17FFF

H'08000

H'0FFFF

H'00000

H'07FFF

Table 3–6. Address Range for Sectors in EPCS4 (Part 2 of 2)

Sector

Address Range (Byte Addresses in HEX)

Start

End

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