PSD833F2 datasheet(84/128 Pages) STMICROELECTRONICS

84 / 128 page

Power management

PSD8XXFX

84/128

Doc ID 7833 Rev 7

17.5

PSD Chip Select input (CSI, PD2)

PD2 of port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When

low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O

blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input

(CSI, PD2) disables the Flash memory, EEPROM, and SRAM, and reduces the PSD power

consumption. However, the PLD and I/O signals remain operational when PSD Chip Select

input (CSI, PD2) is high.

There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on

the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 62

or Table 63.

17.6

Input clock

The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power

consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output macrocells

(OMC).

During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic

equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from

the PLD AND Array or the macrocells block by setting Bits 4 or 5 to a 1 in PMMR0.

17.7

Input control signals

The PSD provides the option to turn off the input control signals (CNTL0, CNTL1, CNTL2,

Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC power consumption. These

control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of

them are not being used as part of the PLD logic equation, these control signals should be

disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits

2, 3, 4, 5, and 6 to a 1 in PMMR2.

Table 33.

APD counter operation

APD Enable

bit

ALE PD

polarity

ALE level

APD counter

Not counting

Pulsing

Not counting

Counting (generates PDN after 15 clocks)

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