PSD833F2 datasheet(86/128 Pages) STMICROELECTRONICS

86 / 128 page

Reset timing and device status at reset

PSD8XXFX

86/128

Doc ID 7833 Rev 7

Figure 33.

Reset (RESET) timing

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

Table 34.

Status during Power-on reset, Warm reset and Power-down mode

Port configuration

Power-on reset

Warm reset

Power-down mode

MCU I/O

Input mode

Unchanged

PLD Output

Valid after internal PSD

configuration bits are

loaded

Valid

Depends on inputs to PLD

(addresses are blocked in

PD mode)

Address Out

Tri-stated

Not defined

Data port

Tri-stated

Peripheral I/O

Tri-stated

Power-on reset

Warm reset

Power-down mode

PMMR0 and PMMR2

Cleared to '0'

Unchanged

Macrocells flip-flop status

Cleared to '0' by internal

Power-On Reset

Depends on .re and .pr

equations

Depends on .re and .pr

equations

VM register(1)

Initialized, based on the

selection in PSDsoft

Configuration menu

Initialized, based on the

selection in PSDsoft

Configuration menu

Unchanged

All other registers

Cleared to '0'

Unchanged

The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset.

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