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L6730 데이터시트(PDF) 21 Page - STMicroelectronics |
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L6730 데이터시트(HTML) 21 Page - STMicroelectronics |
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21 / 52 page ![]() L6730 - L6730B Device description Doc ID 11938 Rev 3 21/52 negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. 5.8 Monitoring and protection The output voltage is monitored by the FB pin. If it is not within ±10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can be delayed by adding an external capacitor on PGDelay pin (see Table 4: Pin connection and Figure 14.); this can be useful to perform cascade sequencing. The delay can be calculated with the following formula: The device provides over voltage protection: when the voltage sensed on FB pin reaches a value 20% (typ) greater than the reference, the low-side driver is turned on. If the OVP not- latched mode has been set the low-side MOSFET is kept on as long as the overvoltage is detected (see Figure 15.).The OVP latched-mode has been set the low-side MOSFET is Figure 13. Dead times ( ) pF C PGDelay ⋅ = 5 . 0 |
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