MPC8315ECVRAGDA datasheet(77/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

SPI

Figure 56 provides the AC test load for the SPI.

Figure 56. SPI AC Test Load

Figure 57 and Figure 58 represents the AC timing from Table 67. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 57 shows the SPI timing in slave mode (external clock).

Figure 57. SPI AC Timing in Slave Mode (External Clock) Diagram

SPI inputs—slave mode (external clock) input setup time

tNEIVKH

4—

SPI inputs—slave mode (external clock) input hold time

tNEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal

timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Table 67. SPI AC Timing Specifications 1

Characteristic

Symbol 2

Min

Max

Unit

Output

Z0 = 50 Ω

NVDD/2

RL = 50 Ω

SPICLK (Input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

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