MPC8315ECVRAGDA datasheet(106/112 Pages) FREESCALE

106 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

106

Freescale Semiconductor

System Design Information

lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint

lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (45

Newtons). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted

or plastic surfaces and its performance verified under the application requirements.

25.3.1

Experimental Determination of the Junction Temperature with a

Heat Sink

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink temperature and

then back calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction to case

thermal resistance.

TJ = TC + (RθJC x PD)

Where

TC is the case temperature of the package

RθJC is the junction-to-case thermal resistance

PD is the power dissipation

26 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8315E.

26.1

System Clocking

The MPC8315E includes two PLLs.

1. The platform PLL (AVDD2) generates the platform clock from the externally supplied

SYS_CLKIN input. The frequency ratio between the platform and SYS_CLKIN is selected using

the platform PLL ratio configuration bits as described in Section 24.1, “System PLL

Configuration.”

2. The e300 Core PLL (AVDD1) generates the core clock as a slave to the platform clock. The

frequency ratio between the e300 core clock and the platform clock is selected using the e300

PLL ratio configuration bits as described in Section 24.2, “Core PLL Configuration.”

26.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins

(AVDD1,AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably

these voltages are derived directly from VDD through a low frequency filter scheme such as the following.

MPC8315ECVRAGDA 데이터시트(PDF) 106 Page - Freescale Semiconductor, Inc