SC28L201 datasheet(70/110 Pages) NXP

70 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

70 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.5.3 Current Interrupt Register (CIR)

The Current Interrupt Register is provided to speed up the speciﬁcation of the interrupting

condition in the UART. The CIR is updated at the beginning of an interrupt acknowledge

bus cycle or in response to an Update CIR command (see Section 8.5.2). Although

interrupt arbitration continues in the background, the current interrupt information remains

frozen in the CIR until another IACKN cycle or Update CIR command occurs. The LSBs of

the CIR provide part of the addressing for various Global Interrupt registers including the

GIBCR, GICR, GITR and the Global RxFIFO and TxFIFO FIFO. The host CPU need not

generate individual addresses for this information since the interrupt context will remain

stable at the ﬁxed addresses of the Global Interrupt registers until the CIR is updated. For

most interrupting sources, the data available in the CIR alone will be sufﬁcient to set up a

service routine.

The CIR may be processed as follows:

If CIR[7] = 1, then a receiver interrupt is pending and the count is CIR[5:1], channel is

CIR[0]

Else if CIR[6] = 1 then a transmitter interrupt is pending and the count is CIR[5:1],

channel is CIR[0]

Table 48:

CIR - Current Interrupt Register (address 0x61) bit description

Bit

Symbol

Description

7:6

Type

00 = type other than transmit or Receiver

01 = transmit

10 = receive without errors

11 = receive with errors

5:1

Current byte count/type. When CIR[7:6] = 00:

0 0000 = no interrupt

0 0001 = change-of-state

0 0010 = address recognition

0 0011 = Xon/Xoff status

0 0100 = Receiver watchdog

0 0101 = break change

0 0110 = Counter/Timer

0 0111 = Rx Loopback error

Current count code. When CIR[7:6] = 01, 10, or 11:

0 0000 => at least 1 character

0 0001 => at least 16 characters

0 0010 => at least 24 characters

…

1 1101 => at least 240 characters

1 1110 => at least 248 characters

1 1111 => 256 (see also Section 8.5.6 “Global Interrupting Byte Count

Channel number or C/T number

0 = Channel A or C/T 0

1 = C/T 1

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