| 전자부품 데이터시트 검색엔진 |
|
MPC8535E 데이터시트(PDF) 120 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8535E 데이터시트(HTML) 120 Page - Freescale Semiconductor, Inc |
|
120 / 126 page ![]() MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Guidelines for High-Speed Interface Termination Freescale Semiconductor 120 The following pins must be connected to XGND if not used: • SD1_RX[7:4] • SD1_RX[7:4] • SD1_REF_CLK • SD1_REF_CLK 3.11.3 SerDes 2 Interface Entirely Unused If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this section. There are several Reserved pins that need to be either left floating or connected to X2GND. See SerDes2 in Table 1Table 1 for details. The following pins must be left unconnected (float): • SD2_TX[0] • SD2_TX[0] • Reserved pins L8, L9 The following pins must be connected to X2GND: • SD2_RX[0] • SD2_RX[0] • SD2_REF_CLK • SD2_REF_CLK The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered. 4 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbers Fully Addressed by This Document.” |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |