MPC8544E datasheet(73/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

PCI Express

17 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8544.

17.1

DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 16.2, “SerDes Reference Clocks.”

17.2

AC Requirements for PCI Express SerDes Clocks

Table 58 provides the AC requirements for the PCI Express SerDes clocks.

17.3

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

17.4

Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer please refer to the

PCI Express Base Specification. Rev. 1.0a.

Table 58. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol2

Parameter Description

Min

Typ

Max

Units

Notes

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any

two adjacent REFCLK cycles

——

100

—

tREFPJ

Phase jitter. Deviation in edge location with respect to

mean edge location

–50

—

Notes:

1. Typical based on PCI Express Specification 2.0.

2. Guaranteed by characterization.

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