MIC3003GML datasheet(8/75 Pages) MICREL

8 / 75 page

Micrel, Inc.

MIC3003

November 2009

M9999-111209-C

hbwhelp@micrel.com or (408) 955-1690

Pin Configuration

24-Pin MLF

® (MLF-24)

Pin Description

Pin Number

Pin Name

Pin Function

Analog Input. Feedback voltage for the APC loop op-amp. Polarity and scale are programmable

via the APC configuration bits I OEMCFG1. Connect to VBIAS if APC is not used.

VMPD

Analog Input. Multiplexed A/D converter input for monitoring transmitted optical power via a

monitor photodiode. In most applications, VMPD will be connected directly to FB. The input range

is 0 - VREF or 0 - VREF/4 depending upon the setting of the APC configuration bits

GNDA

Ground return for analog functions.

VDDA

Power supply input for analog functions.

VILD–

Analog Input. Reference terminal for the multiplexed pseudo-differential A/D converter inputs for

monitoring laser bias current via a sense resistor (VILD+ is the sensing input). Tie to VDD or GND

to reference the voltage sensed on VILD+ to VDD or GND, respectively.

VILD+

Analog Input. Multiplexed A/D input for monitoring laser bias current via a sense resistor (signal

input); accommodates inputs referenced to VDD or GND (see pin 5 description).

SHDN/TXFIN

Digital output/Input; programmable polarity. When used as shutdown output (SHDN), OEMCFG3

bit 2 set to 0, SHDN is asserted at the detection of a fault condition if OEMCFG4 bit 7 is set to 0. If

OEMCFG4 bit 7 is set to 1, a fault condition will not assert SHDN. When programmed as TXFIN, it

is an input for external fault signals to be ORed with the internal fault sources to drive TXFAULT.

VRX

Analog Input. Multiplexed A/D converter input for monitoring received optical power. The input

range is 0 to VREF. A 5-bit programmable EEPOT on this pin provides coarse calibration and

ranging of the RX power measurement.

RS1

Digital Input; Transmitter Rate Select Input; ORed with soft rate select bit SRS1 to determine the

state of the TRSOUT pin. The state of this pin is always reflected in the RS1S bit.

TXFAULT

Digital Output; Open-Drain, with programmable polarity. If OEMCFG5 bit 4 is set to 0, a high level

indicates a hardware fault impeding transmitter operation. If OEMCFG5 bit 4 is set to 1, a low level

indicates a hardware fault impeding transmitter operation. The state of this pin is always reflected

in the TXFLT bit.

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