MCP3901 datasheet(38/62 Pages) MICROCHIP

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MCP3901

DS22192D-page 38

6.9

Data Ready Pin (DR)

To signify when channel data is ready for transmission,

the data ready signal is available on the Data Ready pin

(DR) through an active-low pulse at the end of a

channel conversion.

The data ready pin outputs an active-low pulse with a

period that is equal to the DRCLK clock period, and

with a width equal to one DMCLK period.

When not active-low, this pin can either be in high-

impedance (when DR_HIZN = 0) or in a defined logic

high state (when DR_HIZN = 1). This is controlled

through the Configuration registers. This allows

multiple devices to share the same data ready pin (with

a pull-up resistor connected between DR and DVDD) in

3-phase, energy meter designs to reduce pin count. A

single device on the bus does not require a pull-up

resistor.

After a data ready pulse has occurred, the ADC output

data can be read through SPI communication. Two sets

of latches at the output of the ADC prevent the

communication from outputting corrupted data (see

Section 6.10 “Data Ready Latches and Data Ready

Modes (DRMODE<1:0>)”).

The CS pin has no effect on the DR pin, which means

even if CS is high, data ready pulses will be provided

(except when the configuration prevents them from

outputting data ready pulses). The DR pin can be used

as an interrupt when connected to an MCU or DSP.

While the RESET pin is low, the DR pin is not active.

6.10

Data Ready Latches and Data

Ready Modes (DRMODE<1:0>)

To ensure that both channels’ ADC data is present at

the same time for SPI read, regardless of phase delay

settings for either or both channels, there are two sets

of latches in series with both the data ready and the

‘read start’ triggers.

The first set of latches holds each output when the data

is ready and latches both outputs together when

DRMODE<1:0> = 00. When this mode is on, both

ADCs work together and produce one set of available

data after each data ready pulse (that corresponds to

the lagging ADC data ready). The second set of latches

ensures that when reading starts on an ADC output, the

corresponding data is latched so that no data

corruption can occur.

If an ADC read has started, in order to read the

following ADC output, the current reading needs to be

completed (all bits must be read from the ADC Output

Data registers).

6.10.1

DATA READY PIN (DR) CONTROL

USING DRMODE BITS

There are four modes that control the data ready

pulses

and

these

modes

are

set

with

the

DRMODE<1:0> bits in the STATUS/COM register. For

power metering applications, DRMODE<1:0> = 00 is

recommended (Default mode).

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