MPC5675K datasheet(2/140 Pages) FREESCALE

2 / 140 page

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Overview

Freescale Semiconductor

1.1

Device comparison

Table 1. MPC5675K family device comparison

Features

MPC5673K

MPC5674K

MPC5675K

CPU

Type

2 × e200z7d (SoR1) in lock-step or decoupled operation

Architecture

Harvard

Execution speed

0–150 MHz (+2% FM)

0–180 MHz (+2% FM)

Nominal platform

frequency (in 1:1, 1:2,

and 1:3 modes)

0–75 MHz (+2% FM)

0–90 MHz (+2% FM)

MMU

64 entries (SoR)

Instruction set PPC

Yes

Instruction set VLE

Yes

Instruction cache

16 KB, 4-way with EDC (SoR)

Data cache

16 KB, 4-way with EDC (SoR)

MPU

Yes (SoR)

Buses

Core bus

32-bit address, 64-bit data

Internal periphery bus

32-bit address, 32-bit data

XBAR

Master

 slave ports

Yes (SoR)

Memory

Static RAM (SRAM)

256 KB (ECC)

384 KB (ECC)

512 KB (ECC)

Code Flash memory

1MB2

1.5 MB2

2MB2

Data Flash memory

64 KB2

Modules

Analog-to-Digital

Converter (ADC)

257 pin pkg: 4 × 12 bit (22 external channels)

473 pin pkg: 4 × 12 bit (up to 34 external channels)

CRC unit

2 (3 contexts each)

Cross Triggering Unit

(CTU)

2 modules

Deserial Serial

Peripheral Interface

(DSPI)

2 modules

(3 chip selects)

3 modules

(3 chip selects)

Digital I/Os

 16

DRAM Controller

(DRAMC)

Yes3

Enhanced Direct

Memory Access (eDMA)

2 modules, 32 channels each

eTimer

3 modules, 6 channels each

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