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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC5673K 데이터시트(PDF) 80 Page - Freescale Semiconductor, Inc |
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MPC5673K 데이터시트(HTML) 80 Page - Freescale Semiconductor, Inc |
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80 / 140 page  MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Electrical characteristics Freescale Semiconductor 80 tLOCK P Lock time Stable oscillator (fPLLIN = 4 MHz), stable VDD — — 200 µs tlpll D FMPLL lock time 5, 6 —— — TBD s tdc D Duty cycle of reference —40 — 60 % CJITTER T CLKOUT period jitter7,8,9,10 Peak-to-peak (clock edge to clock edge), fSYS maximum TBD — TBD ps Long-term jitter (avg. over 2 ms interval), fSYS maximum TBD — TBD ns t PKJIT T Single period jitter (peak to peak) PHI @ 16 MHz, Input clock @ 4 MHz —— ±500 ps t LTJIT T Long term jitter PHI @ 16 MHz, Input clock @ 4 MHz —— ±6 ns fLCK D Frequency LOCK range — TBD — TBD % fsys fUL D Frequency un-LOCK range — TBD — TBD % fsys fCS fDS D Modulation Depth Center spread TBD — TBD % fsys Down Spread TBD — TBD fMOD D Modulation frequency11 — TBD — TBD kHz NOTES: 1 Considering operation with FMPLL not bypassed. 2 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked mode. 3 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the fLOR window. 4 f VCO is the frequency at the output of the VCO; its range is 256–512 MHz. fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz. fSYS =fVCOODF 5 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this FMPLL, load capacitors should not exceed these limits. 6 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 7 This value is determined by the crystal manufacturer and board design. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 9 Proper PC board layout procedures must be followed to achieve specifications. 10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C JITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 11 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz. Table 22. FMPLL electrical characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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