MPC5673K datasheet(124/140 Pages) FREESCALE

124 / 140 page

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

124

Figure 51. MII receive signal timing diagram

3.22.8.2

MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the system clock frequency must exceed four times the

TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising

or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of

non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Figure 52. MII transmit signal timing diagram

Table 70. MII transmit signal timing1

NOTES:

1 Output pads configured with SRC = 0b11.

No.

Parameter

Min

Max

Unit

TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

5—

TX_CLK to TXD[3:0], TX_EN, TX_ER valid

—25

TX_CLK pulse width high

40%

60%

TX_CLK period

TX_CLK pulse width low

40%

60%

TX_CLK period

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

TX_CLK (input)

TXD[3:0] (outputs)

TX_EN

TX_ER

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