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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC5673K 데이터시트(PDF) 130 Page - Freescale Semiconductor, Inc |
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MPC5673K 데이터시트(HTML) 130 Page - Freescale Semiconductor, Inc |
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130 / 140 page  MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Electrical characteristics Freescale Semiconductor 130 3.22.10 I2C Timing Table 74. I2C SCL and SDA input timing specifications No. Symbol Parameter Value Unit Min Max 1 — D Start condition hold time 2 — IP bus cycle1 NOTES: 1 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. 2 — D Clock low time 8 — IP bus cycle1 4 — D Data hold time 0.0 — ns 6 — D Clock high time 4 — IP bus cycle1 7 — D Data setup time 0.0 — ns 8 — D Start condition setup time (for repeated start condition only) 2 — IP bus cycle1 9 — D Stop condition setup time 2 — IP bus cycle1 Table 75. I2C SCL and SDA output timing specifications No. Symbol Parameter Value Unit Min Max 11 NOTES: 1 Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. — D Start condition hold time 6 — IP bus cycle2 2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. 21 — D Clock low time 10 — IP bus cycle1 33 3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. — D SCL/SDA rise time — 99.6 ns 41 — D Data hold time 7 — IP bus cycle1 51 — D SCL/SDA fall time — 99.5 ns 61 — D Clock high time 10 — IP bus cycle1 71 — D Data setup time 2 — IP bus cycle1 81 — D Start condition setup time (for repeated start condition only) 20 — IP bus cycle1 91 — D Stop condition setup time 10 — IP bus cycle1 |
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