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PIC24F04KA201 데이터시트(PDF) 9 Page - Microchip Technology

부품명 PIC24F04KA201
상세설명  Flash Programming Specifications
PDF  48 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

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Advance Information
DS39919A-page 9
3.4
Flash Memory Programming in
ICSP Mode
3.4.1
PROGRAMMING OPERATIONS
The NVMCON register controls the Flash memory write
and erase operations. To program the device, set the
NVMCON register to select the type of erase operation
(see Table 3-2) or write operation (see Table 3-3). Set
the WR control bit (NVMCON<15>) to initiate the
program.
In ICSP mode, all programming operations are
self-timed. There is an internal delay between setting
and automatic clearing of the WR control bit when the
programming
operation
is complete.
Refer
to
Section 7.0 “AC/DC Characteristics and Timing
Requirements”
for
information
on
the
delays
associated with various programming operations.
TABLE 3-3:
NVMCON VALUES FOR
WRITE OPERATIONS
3.4.2
STARTING AND STOPPING A
PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Initiate the programming cycle by setting
the WR bit.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
is completed. Start a programming cycle as follows:
BSET
NVMCON, #WR
3.5
Erasing Program Memory
To erase the program memory (all of code memory,
data memory and Configuration bits, including the
code-protect bits), set the NVMCON to 4064h and then
execute the programming cycle.
Figure 3-6 illustrates the ICSP programming process
for Bulk Erase. This process includes the ICSP
command code, which must be transmitted (for each
instruction), LSB first, using the PGCx and PGDx pins
(see Figure 3-2).
Table 3-4 provides the steps for executing serial
instruction for the Bulk Erase mode.
FIGURE 3-6:
BULK ERASE FLOW
TABLE 3-2:
NVMCON VALUES FOR
ERASE OPERATIONS
NVMCON
Value
Erase Operation
4064h
Erase the code memory and
Configuration registers (does not erase
programming executive code and
Device ID registers).
404Ch
Erase the general segment and
Configuration bits associated with it.
4068h
Erase the boot segment and
Configuration bits associated with it.
405Ah(1)
Erase four rows of code memory.
4059h(1)
Erase two rows of code memory.
4058h(1)
Erase a row of code memory.
4050h
Erase the entire data EEPROM
memory and Configuration bits
associated with it.
405Ah(1)
Erase eight words of data EEPROM
memory.
4059h(1)
Erase four words of data EEPROM
memory.
4058h(1)
Erase one word of data EEPROM
memory.
4054h
Erase all the Configuration registers
(except the code-protect fuses).
4058h(1)
Erase Configuration registers except
FBS and FGS.
Note 1:
The destination address decides the
region (code memory, data EEPROM
memory or Configuration register) of the
erased rows/words.
NVMCON
Value
Write Operation
4004h(1)
Write one Configuration register.
4004h(1)
Program one row (32 instruction words)
of code memory or executive memory.
4004h(1)
Program one word of data EEPROM
memory.
Note 1:
The destination address decides the
region (code memory, data EEPROM
memory or Configuration register) of the
erased rows/words.
Note:
Program memory must be erased before
writing any data to program memory.
End
Set the WR bit to Initiate Erase
Write 4064h to NVMCON SFR
Delay P11 + P10 Time
Start



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