SYSTEM MANAGEMENT

ACT5830

Rev 2, 20-Jan-11

Innovative Power

TM

- 9 -

www.active-semi.com

Copyright © 2010 Active-Semi, Inc.

ActivePMU

I

®

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PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SCL, SDA Low Input Voltage

0.4

V

SCL, SDA High Input Voltage

1.4

V

SCL, SDA Leakage Current

1

µA

SDA Low Output Voltage

0.3

V

2.5

µs

100

ns

300

ns

Start Condition

100

ns

Stop Condition

100

ns

Figure 1:

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Note: Each session of data transfer is with a start condition, a 7-bits slave address plus a bit to instruct for read or write followed by an

acknowledge bit, a register address byte followed by an acknowledge bit, a data byte followed by an acknowledge bit and a stop condi-

tion. The device address, the register address and the data are all MSB first transferred. Each bit volume is prepared in during the SCL

is low, is latched-in by the rising edge of the SCL. The data byte is accepted and is put effective by the time that the last bit volume is

latched-in.