TMS570LS3137 datasheet(113/159 Pages) TI

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tcyc(DMM)

th(DMM)

tl(DMM)

DMMSYNC

DMMCLK

DMMDATA

ssu(DMM)

sh(DMM)

dsu(DMM)

dh(DMM)

TMS570LS3137

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SPNS162.

– SEPTEMBER 2011

4.21.9 Data Modification Module (DMM)

The Data Modification Module (DMM) provides the capability to modify data in the entire 4 GB address

space of the TMS570 devices from an external peripheral, with minimal interruption of the application.

4.21.9.1 Features

The DMM module has the following features:

•

Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention

•

Writes to memory locations specified in the received packet (leverages packets defined by trace mode

of the RAM trace port (RTP) module

•

Writes received data to consecutive addresses, which are specified by the DMM module (leverages

packets defined by direct data mode of RTP module)

•

Configurable port width (1, 2, 4, 8, 16 pins)

•

Up to 100 Mbit/s pin data rate

•

Unused pins configurable as GIO pins

4.21.9.2 Timing Specifications

Figure 4-27. DMMCLK Timing

Table 4-46. DMMCLK Timing

Parameter

MIN

Description

tcyc(DMM)

tc(HCLK) * 2

Clock period

th(DMM)

((tcyc(DMM))/2) - ((tr+tf)/2)

High pulse width

tl(DMM)

((tcyc(DMM))/2) - ((tr+tf)/2)

Low pulse width

Figure 4-28. DMMDATA Timing

System Information and Electrical Specifications

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