TMS570LS3137 datasheet(117/159 Pages) TI

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TMS570LS3137

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SPNS162.

– SEPTEMBER 2011

•

Programmable interrupt threshold counter is available for each group

•

Programmable magnitude threshold interrupt for each group for any one channel

•

Option to read either 8-bit, 10-bit or 12-bit values from memory regions

•

Single or continuous conversion modes

•

Embedded self-test

•

Embedded calibration logic

•

Enhanced power-down mode

– Optional feature to automatically power down ADC core when no conversion is in progress

•

External event pin (ADEVT) programmable as general-purpose I/O

5.2.2

Event Trigger Options

The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3

groups can be configured to be hardware event-triggered. In that case, the application can select from

among 8 event sources to be the trigger for a group's conversions.

5.2.2.1

Default MIBADC1 Event Trigger Hookup

Table 5-3. MIBADC1 Event Trigger Hookup

Event #

Source Select Bits For G1, G2 Or Event

Trigger

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

000

ADEVT

001

N2HET1[8]

010

N2HET1[10]

011

RTI compare 0 interrupt

100

N2HET1[12]

101

N2HET1[14]

110

GIOB[0]

111

GIOB[1]

NOTE

For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module

trigger input is made from the output side of the input buffer. This way, a trigger condition

can be generated either by configuring the function as output onto the pad (via the mux

control), or by driving the function from an external trigger source as input. If the mux control

module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x]

signals, then care must be taken to disable these signals from triggering conversions; there

is no multiplexing on the input connections.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

5.2.2.2

Alternate MIBADC1 Event Trigger Hookup

Table 5-4. Alternate MIBADC1 Event Trigger Hookup

Event #

Source Select Bits for G1, G2 or Event

Trigger

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

000

ADEVT

001

N2HET2[5]

Peripheral Information and Electrical Specifications

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