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TMS570LS3137 데이터시트(PDF) 145 Page - Texas Instruments |
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TMS570LS3137 데이터시트(HTML) 145 Page - Texas Instruments |
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145 / 159 page ![]() SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid 3 2 1 5 4 6 6 7 SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid 9 SPICLK (clock polarity=1) SPIENAn 10 Write to buffer 11 8 TMS570LS3137 www.ti.com SPNS162. – SEPTEMBER 2011 Figure 5-10. SPI Master Mode External Timing (CLOCK PHASE = 0) Figure 5-11. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0) Copyright © 2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 145 Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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