TMS570LS3137 datasheet(148/159 Pages) TI

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TMS570LS3137

SPNS162.

– SEPTEMBER 2011

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5.10.5 SPI Slave Mode I/O Timings

Table 5-25. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =

input, and SPISOMI = output)(1)(2)(3)(4)

NO.

Parameter

MIN

MAX

Unit

tc(SPC)S

Cycle time, SPICLK(5)

256tc(VCLK)

2(6)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

3(6)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

4(6)

td(SPCH-SOMI)S

Delay time, SPISOMI valid after SPICLK high (clock

trf(SOMI) + 18

polarity = 0)

td(SPCL-SOMI)S

Delay time, SPISOMI valid after SPICLK low (clock polarity

trf(SOMI) + 18

= 1)

5(6)

th(SPCH-SOMI)S

Hold time, SPISOMI data valid after SPICLK high (clock

polarity =0)

th(SPCL-SOMI)S

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

6(6)

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity =

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity =

7(6)

th(SPCL-SIMO)S

Hold time, SPISIMO data valid after SPICLK low (clock

polarity = 0)

th(SPCH-SIMO)S

Hold time, SPISIMO data valid after S PICLK high (clock

polarity = 1)

td(SPCL-SENAH)S

Delay time, SPIENAn high after last SPICLK low (clock

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn)

polarity = 0)

td(SPCH-SENAH)S

Delay time, SPIENAn high after last SPICLK high (clock

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn)

polarity = 1)

td(SCSL-SENAL)S

Delay time, SPIENAn low after SPICSn low (if new data

tf(ENAn)

tc(VCLK)+tf(ENAn)+1

has been written to the SPI buffer)

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2)

If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3)

For rise and fall timings, see the

"switching characteristics for output timings versus load capacitance" table.

(4)

tc(VCLK) = interface clock cycle time = 1 /f(VCLK)

(5)

When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.

(6)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

148

Peripheral Information and Electrical Specifications

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