Rev. 1.00

5

November 16, 2011

HT16L21

Timing Diagrams

SDA

SCL

S

Sr

P

S

SDA

OUT

SPI timing

DIO

(INPUT )

CLK

CSB

10%

DIO

(OUTPUT )

90%

90%

90%

90%

90%

90%

90%

90%

90%

90%

10%

10%

10%

10%

10%

10%

10%

10%

10%

Reset timing

VDD

Data

transfer

50%

0.9V

0.9V

50%

80%

RSTB

50%

50%

50%

50%

50%

Note:1.IftheconditionsofresettimingarenotsatisfiedinpowerON/OFFsequence,theinternalpoweronreset

(POR)circuitwillnotoperatenormally.

risingtothenormaloperatingvoltage.

thepower-onsequencetoensurethattheresetoperationiscomplete.