Rev. 1.00

17

November 16, 2011

HT16L21

differentICsormodules.Thetwolinesareaserialdataline,SDA,andaserialclockline,SCL.Bothlinesare

connectedtothepositivesupplyviapull-upresistorswithatypicalvalueof4.7KΩ.Whenthebusisfree,both

linesarehigh.Devicesconnectedtothebusmusthaveopen-drainoropen-collectoroutputstoimplementawired-

orfunction.Datatransferisinitiatedonlywhenthebusisnotbusy.

Data validity

ThedataontheSDAlinemustbestableduringthehighperiodoftheserialclock.Thehighorlowstateofthe

datalinecanonlychangewhentheclocksignalontheSCLlineisLowasshowninthediagram.

SDA

SCL

Datalinestable;

Datavalid

Changeofdata

allowed

START and STOP conditions

• AhightolowtransitionontheSDAlinewhileSCLishighdefinesaSTARTcondition.

• AlowtohightransitionontheSDAlinewhileSCLishighdefinesaSTOPcondition.

• STARTandSTOPconditionsarealwaysgeneratedbythemaster.Thebusisconsideredtobebusyafterthe

STARTcondition.ThebusisconsideredtobefreeagainacertaintimeaftertheSTOPcondition.

• ThebusstaysbusyifarepeatedSTART(Sr)isgeneratedinsteadofaSTOPcondition.Insomerespects,the

START(S)andrepeatedSTART(Sr)conditionsarefunctionallyidentical.

P

S

SDA

SCL

SDA

SCL

STARTcondition

STOPcondition

Byte format

EverybyteputontheSDAlinemustbe8-bitlong.Thenumberofbytesthatcanbetransmittedpertransferis

unrestricted.Eachbytehastobefollowedbyanacknowledgebit.Dataistransferredwiththemostsignificantbit,

MSB,first.

S

or

Sr

P

or

Sr

SDA

SCL

1

2

7

8

9

ACK

1

2

3-8

9

ACK

P

Sr