Rev. 1.00

13

November 16, 2011

HT16L21

24×4 Display Mode

WhentheSP1bitissetto“1”andtheSP0bitissetto“1”,thedrivemodeisselectedas24segmentsby

4commonstogetherwith8LEDdrivingoutputs.

Output

COM3

COM2

COM1

COM0

Output

COM3

COM2

COM1

COM0 Address

SEG1

—

—

—

—

SEG0

—

—

—

—

00H

SEG3

—

—

—

—

SEG2

—

—

—

—

01H

SEG5

—

—

—

—

SEG4

—

—

—

—

02H

↓

↓

↓

↓

↓

↓

↓

↓

↓

↓

↓

SEG23

—

—

—

—

SEG22

—

—

—

—

0BH

—

D7

D6

D5

D4

—

D3

D2

D1

D0

Data

RAM mapping of 24×4 display mode

System Oscillator

ThetimingfortheinternallogicandtheLCDdrivesignalsaregeneratedbyaninternaloscillator.TheSystem

willbeinthestopstate.

LCD Bias Generator

TheLCDsupplypowercancomefromtheexternalVLCDpinortheinternalregulatoroutputvoltagedetermined

usingtheInternalVoltageAdjustment(IVA)settingcommand.ThedeviceprovidesanexternalVLCDpinand

alsointegratesaninternalregulator.TheLCDvoltagemaybetemperaturecompensatedexternallythroughthe

VoltagesupplytotheVLCDpin.TheinternalregulatorcanalsoprovidetheLCDoperatingvoltage.Therefore,

FractionalLCDbiasingvoltages,knownas1/2or1/3biasvoltage,areobtainedfromaninternalvoltagedividerof

a1/2biasvoltagelevelconfiguration.