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AFS090 데이터시트(PDF) 232 Page - Microsemi Corporation |
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AFS090 데이터시트(HTML) 232 Page - Microsemi Corporation |
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232 / 334 page ![]() Device Architecture 2- 21 6 R e v isio n 2 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-136 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Core Array Data Input I/O Register with Active High Enable Active High Clear Positive Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive Edge Triggered CLK Enable CLR Data_out Data Y AA EOUT DOUT DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR BB CC DD EE FF GG LL HH JJ KK INBUF INBUF CLKBUF |
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