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CY7C09279V-7AXC 데이터시트(PDF) 13 Page - Cypress Semiconductor

부품명 CY7C09279V-7AXC
상세설명  3.3 V 16 K / 32 K / 64 K 횞 16 / 18 Synchronous Dual-Port Static RAM
PDF  22 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C09279V-7AXC 데이터시트(HTML) 13 Page - Cypress Semiconductor

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CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *I
Page 13 of 22
Figure 11. Flow Through Read-to-Write-to-Read (OE = VIL)
[35, 36, 37, 38]
Figure 12. Flow Through Read-to-Write-to-Read (OE Controlled) [35, 36, 37, 38, 39]
Switching Waveforms (continued)
tCH1
tCL1
tCYC1
tSC
tHC
tSW
tHW
tSA
tHA
tSW
tHW
tSD
tHD
An
An+1
An+2
An+2
An+3
An+4
Dn+2
Qn
Qn+1
Qn+3
tCD1
tCD1
tDC
tCKHZ
tCD1
tCD1
tCKLZ
tDC
READ
NO
OPERATION
WRITE
READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
Qn
tCH1
tCL1
tCYC1
tSC
tHC
tSW
tHW
tSA
tHA
tCD1
tDC
tOHZ
READ
An
An+1
An+2
An+3
An+4
An+5
Dn+2
Dn+3
tSW
tHW
tSD
tHD
tCD1
tCD1
tCKLZ
tDC
Qn+4
tOE
WRITE
READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
OE
Notes
35. ADS = VIL, CNTEN and CNTRST = VIH.
36. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
37. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
38. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
39. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.



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