ADS5294IPFPR datasheet(28/67 Pages) TI1

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SDATA

SCLK

CSZ

SDOUT

A) Enable Serial Readout (<READOUT> = 1)

Pin SDOUT is tri-stated

Pin SDOUT Becomes

Active and Forces Low

SDATA

SCLK

CSZ

SDOUT

B) Read Contents of Register 0x0F.

This Register has been Initialized with 0x0200

(The Device was earlier put in global power down)

D15 D14 D13 D12 D11 D10 D9

SDOUT Output Contents of Register 0x0F in the same cycle, MSB first

ADS5294

SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

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Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back on SDOUT pin. This

may be useful as a diagnostic check to verify the serial interface communication between the external controller

and the ADC.

By default, after power up and device reset, the SDOUT pin is in the high-impedance state. When the readout

mode is enabled using the register bit <READOUT>, SDOUT outputs the contents of the selected register

serially, described as follows.

•

Set register bit <READOUT> = 1 to put the device in serial readout mode. This disables any further writes

into the internal registers, EXCEPT the register at address 1. Note that the <READOUT> bit itself is also

located in register 1.

The device can exit readout mode by writing <READOUT> to 0.

Only the contents of register at address 1 cannot be read in the register readout mode.

•

Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content is to be read.

•

The device serially outputs the contents (D15–D0) of the selected register on the SDOUT pin.

•

The external controller can latch the contents at the rising edge of SCLK.

•

To exit the serial readout mode, reset register bit <READOUT> = 0, which enables writes into all registers of

the device. At this point, the SDOUT pin enters the high-impedance state.

Figure 46. Serial Readout Timing

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