ADS5294IPFPR datasheet(53/67 Pages) TI1

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CLKP

5 kΩ

VCM

5 kΩ

6 pF

5 Ω

Lpkg

~ 2 nH

Cbond

~ 0.5 pF

Lpkg

~ 2 nH

Cbond

~ 0.5 pF

Resr

~ 200 Ω

Resr

~ 200 Ω

CLKM

Clock buffer

Ceq

6 pF

0.1 F

10 W

2 pF

10 W

0.1 F

Differential

Input

INP

INM

ADS259x

ADS5294

www.ti.com

SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

Figure 57. Analog Input Drive Circuit

Large and Small Signal Input Bandwidth

The small signal bandwidth of the analog input circuit is high, around 550 MHz. When using an amplifier to drive

the ADS5294, the total noise of the amplifier up to the small signal bandwidth must be considered. The large

signal bandwidth of the device depends on the amplitude of the input signal. The ADS5294 supports 2 VPP

amplitude for input signal frequency up to 80 MHz. For higher frequencies (80 MHz), the amplitude of the input

signal must be decreased proportionally. For example, at 160 MHz, the device supports a maximum of 1 VPP

signal.

INPUT CLOCK

The ADS5294 is configured by default to operate with a single-ended input clock – CLKP is driven by a CMOS

clock and CLKM is tied to GND. The device can automatically detect a single-ended or differential clock. If CLKM

is grounded, the device treats clock as a single-ended clock. Operating with a low-jitter differential clock usually

gives better SNR performance, especially at input frequencies greater than 30 MHz. Typical clock termination

structures are listed in Figure 58 andFigure 59.

Ceq is approximately 1 to 3 pF, equivalent input capacitance of clock buffer.

Figure 58. Equivalent Circut of the Input Clock Circuit

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