TLK3114SCZPV datasheet(21/68 Pages) TI1

21 / 68 page

3−3

Byte to be Transmitted

td(T_Latency)

10-Bit Code Transmitted

TXxP

TXxN

TDx[7:0]

TCx

Figure 3−2. Transmitter Latency

3.7

Channel Clock to Serial Transmit Clock Synchronization

The TLK3114SC device requires an external differential reference clock, RFCP/N, for the on-chip phase-locked loop

(PLL) and the clock/data recovery loop. To compensate for arbitrary clock phase tolerance differences between the

reference clock and the data aligned to the transmit clock, a small FIFO in the parallel transmit data path on each

channel is employed. This FIFO has a depth of four bytes.

The reference clock and the transmit data clock(s) are assumed to be from a common source and only phase

misaligned due to different path delays as shown in Figure 3−3 and Figure 3−4. The reference clock is multiplied in

frequency 10x to produce the internal serialization clock. The internal serialization clock is used to clock out the serial

transmit data.

Channel

Logic

Protocol Device

FIFO

Channel A

TCA

TLK3114SC

Serdes

Core

Data A

Channel

Logic

FIFO

Channel B

Data B

Serdes

Core

Channel

Logic

FIFO

Channel C

Data C

Serdes

Core

Channel

Logic

FIFO

Channel D

Data D

Serdes

Core

Xtal OSC

RFCP/RFCN

Figure 3−3. Transmit and Reference Clock Relationship (Channel Sync Mode)

TLK3114SCZPV 데이터시트(PDF) 21 Page - Texas Instruments

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