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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TLK3114SCZPV 데이터시트(PDF) 49 Page - Texas Instruments |
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TLK3114SCZPV 데이터시트(HTML) 49 Page - Texas Instruments |
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49 / 68 page  3−31 Table 3−24. Channel Synchronization Status Register (Register 23) BIT(S) NAME DESCRIPTION READ/WRITE 15:5 Reserved Read returns all 0s. Read-only 4 Channel align flag 1 = Channel deskew circuit has realigned to a K28.3 /A/ code word on all channels. 0 = No /A/ has been detected. After being read, this bit is reset to 0. Read-only 3 Channel D receive FIFO collision error 1 = Collision error is detected to cause the receive FIFO self reset. 0 = No error. After being read, this bit is reset to 0. Read-only 2 Channel C receive FIFO collision error 1 = Collision error is detected to cause the receive FIFO self reset. 0 = No error. After being read, this bit is reset to 0. Read-only 1 Channel B receive FIFO collision error 1 = Collision error is detected to cause the receive FIFO self reset. 0 = No error. After being read, this bit is reset to 0. Read-only 0 Channel A receive FIFO collision error 1 = Collision error is detected to cause the receive FIFO self reset. 0 = No error. After being read, this bit is reset to 0. Read-only |
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