TLK3114SCZPV datasheet(33/68 Pages) TI1

33 / 68 page

3−15

RXAP/RXAN

Any Valid

Code

K28.5

K28.3

K28.0

RXBP/RXBN

RXCP/RXCN

RXDP/RXDN

RCA

RDA[9:0]

RDB[9:0]

RDC[9:0]

RDD[9:0]

Undefined

X X X X X X X X X

A A A A A A A A A

K K K K K K K K K

R R R R R R R R R

K K K

X X X X X X X X X

A A A A A A A A A

K K K K K K K K K

R R R R R R R R R

K K K

X X X X X X X X X

A A A A A A A A A

K K K K K K K K K

R R R R R R R R R

K K K

X X X X X X X X X

A A A A A A A A A

K K K K K K K K K

R R R R R R R R R

K K K

Figure 3−14. Channel Synchronization Using Alignment Code

3.19 Clock Tolerance Compensation (CTC)

The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the reference clocks

for two devices on a XAUI link have the same specified frequencies, there are slight differences within those limits

that, if not compensated for, lead to over- or underruns of the FIFOs on the receive data path. The TLK3114SC device

provides compensation for these differences in reference clock frequencies via the insertion or the removal of R

characters on all channels, as shown in Figure 3−15 and Figure 3−16. Bit 11 of MDIO register 16 allows enabling of

the CTC, as noted in Table 3−18.

TLK3114SCZPV 데이터시트(PDF) 33 Page - Texas Instruments

TLK3114SCZPV 데이터시트(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

데이터시트 다운로드

링크 URL