ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

17

POST OFFICE BOX 1443

timing requirements, PCI 5-V and 3.3-V (see Note 15 and Figure 4) (continued)

5-V Clock

3.3-V Clock

0.8 V

2 V

1.5 V

Output

Delay

3-State

Output

Input

tc

tw(H)

tw(L)

tVAL

ton

tsu

th

Inputs

Valid

VMAX

toff

0.475

× VDD

0.4

× VDD

0.326

× VDD

Figure 4. PCI 5-V and 3.3-V Timing