ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

12

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (PCI interface pins)

PARAMETER

TEST CONDITIONS †

3-V SIGNALING

OPERATION

5-V SIGNALING

OPERATION

UNIT

MIN

MAX

MIN

MAX

VOH

High-level output voltage,

TTL-level signal (see Note 6)

VDD = MIN,

IOH = MAX

0.9

 VDD‡

2.4

V

VOL

Low-level output voltage,

TTL-level signal

VDD = MAX,

IOL = MAX

0.1

 VDD‡

0.5

V

IOZ

High impedance output current

VDD = MAX,

VO = 0 V

10

10

µA

IOZ

High-impedance output current

VDD = MAX,

VO = VDD

–10

– 10

µA

II

Input current, any input or input / output

VI = VSS to VDD

" 10

" 10

µA

IDD

Supply current

VDD = MAX

50

60

mA

Ci

Input capacitance, any input§

f = 1 MHz,

Others at 0 V

10

10

pF

CO

Output capacitance, any output or

input / output§

f = 1 MHz,

Others at 0 V

10

10

pF

† For conditions shown as MIN / MAX, use the appropriate value specified under the recommended operating conditions.

‡ Assured by SPICE IV Curve (see PCI specification revision 2.1, section 4.2, paragraph 2 for explanation)

§ Specified by design

NOTE 6: The following signals require an external pullup resistor: PSERR, PINTA.

recommended operating conditions (logic pins) (see Note 7)

MIN

NOM

MAX

UNIT

VDD Supply voltage (5 V only)

4.75

5

5.25

V

VIH

High-level input voltage

2

VDD + 0.3

V

VIL

Low-level input voltage, TTL-level signal (see Note 4)

– 0.3

0.8

V

IOH

High-level output current

TTL outputs

–4

mA

IOL

Low-level output current (see Note 5)

TTL outputs

4

mA

NOTES:

4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels

only.

5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst

case).

7. Logic pins include VDDL, EAD[7:0], EXLE, EALE, EOE, EDCLK, EDIO.

electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)

(logic pins)

PARAMETER

TEST CONDITIONS †

MIN

NOM

MAX

UNIT

VOH High-level output voltage, TTL-level signal

VDD = MIN,

IOH = MAX

2.4

V

VOL Low-level output voltage, TTL-level signal

VDD = MAX,

IOL = MAX

0.5

V

IO

High impedance output current

VDD = MIN,

VO = VDD

10

µA

IO

High-impedance output current

VDD = MIN,

VO = 0 V

–10

µA

II

Input current

VI = VSS to VDD

"10

µA

IDD

Supply current @ 25 MHz (PCLK)

VDD = NOM

190¶

mA

IDD

Supply current @ 33 MHz (PCLK)

VDD = NOM

228¶

mA

Ci

Input capacitance, any input§

f = 1 MHz,

Others at 0 V

10

pF

Co

Output capacitance, any output or input / output§

f = 1 MHz,

Others at 0 V

10

pF

† For conditions shown as MIN / MAX, use the appropriate value specified under the recommended operating conditions.

§ Specified by design

¶ Characterized in system test not tested