TLC320AD56 datasheet(22/42 Pages) TI1

22 / 42 page

3–2

Figure 3–1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The

timing sequence for this operation is as follows:

FS is brought low by the TLC320AD56C.

One 16-bit word is transmitted from the ADC (DOUT) and one 16-bit word is received for the DAC

(DIN).

FS is brought high by the TLC320AD56C signaling the end of the conversion.

D15

D14

...D2

tdis

SCLK

tsu

td1

ten

D15

D14

...D2

DIN

DOUT

td2

In 16-Bit Mode:

MSB

tsu

D15

D14

...D2

DIN

In 16-Bit Mode:

MSB

LSB

td3

MCLK

0th

1st

2nd

14th

15th

16th

VIH

VIL

VOH

VOL

VOH

VOL

Figure 3–1. Primary Serial Communication Timing

When a secondary request is made through the LSB of the DAC data word (16-bit mode), the format in

Table 3–1 is used.

Table 3–1. Secondary Request Format

D15

D14

D13

D12

D11

D10

15-bit DAC

2’s-complement format

16-bit ADC

2’s-complement format

control

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