3–6

3.3

Conversion Rate vs Serial Port

The SCLK frequency is set by the frequency of MCLK. There is a 2-stage clock divider that sets the SCLK

frequency as MCLK/4.

3.4

Phone Mode Control

Phone mode control is provided for applications that need hardware control and monitoring of external

events. By allowing the device to drive two FLAG terminals (set through the Control 2 register), the host

(DSP) is capable of system control through the same serial port that connects to the device. Along with this

control is the capability of monitoring the value of the ALT DATA terminal during a secondary communication

cycle. One application for this function is in monitoring RING DETECT or OFFHOOK DETECT from a phone

answering system. The two FLAG terminals allow response to these incoming control signals. Figure 3–6

shows the timing associated with this operating mode.

DOUT

(Secondary

Write)

Primary

Secondary

Primary

Secondary

Primary

ALT DATA

ALT DATA

DIN

Set FLAG0 = FLAG1 = 0

FLAG0,

FLAG1

DOUT

(Secondary

Read)

ALT DATA

Register

Data

8 SCLKs

1 SCLK MAX

Set FLAG0 = FLAG1 = 1

FS

Figure 3–5. Phone Mode Timing

DIN

(Secondary

Read)

8 Bits

DIN

(Secondary

Write)

8 Bits

R/W

Register Address

Do Not Care

Data to the

Register

Figure 3–6. Secondary DIN Format