STULPI01A_12 datasheet(8/44 Pages) STMICROELECTRONICS

8 / 44 page

Bump configuration

STULPI01A, STULPI01B

8/44

Doc ID 14817 Rev 4

Bump

Symbol

Type

Description

Not connected

Not connected.

VB_REF_FAULT

Voltage reference for internal OC detector input or digital input from

external OC detector (V3V3V referred). 5 V tolerant.

PSWn

External charge pump control, active low. 5 V tolerant, open drain.

External clock input (VDVIO referred).

XO pin must be left floating or grounded (crystal is not supported).

VBAT

PWR

Battery power input for the LDO (3 V – 4.5 V). Bypass VBAT to GND with

a 1 µF capacitor.

3V3V

PWR

3.3 V LDO output. Bypass 3V3V to GND with a 1.5 µF capacitor.

1V2V

PWR

1.2 V LDO output. Bypass 1V2V to GND with a 1.5 µF capacitor.

RREF

I/O

Reference resistor (12 k

Ω ±1%)

B2/B3/B5

VDVIO

PWR

Digital I/O supply voltage. Bypass each VDVIO to GND with

a 100 nF-1

μF capacitor. Balls B2-B5 can share common capacitor.

C5/D2

GND

PWR

Ground

B4/E4/E1

GND

PWR

Ground

Table 2.

Pinout and bump description (continued)

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