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ST10F276E 데이터시트(PDF) 68 Page - STMicroelectronics |
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ST10F276E 데이터시트(HTML) 68 Page - STMicroelectronics |
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68 / 235 page ![]() Bootstrap loader ST10F276E 68/235 Doc ID 12303 Rev 3 Even if the internal IFLASH is enabled, a code cannot be executed from it. As the XFlash is needed, XPERCON register is configured by the ABM loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. To do this, perform the following steps: 1. Copy in DPRAM a function that will a) disable the XPeripherals by clearing XPEN in SYSCON register, b) enable the needed XPeripherals by writing the correct value in XPERCON register, c) set XPEN bit in SYSCON, d) return to calling address. 2. Call the function from XFlash The changing of the XPERCON value cannot be executed from the XFlash because the XFlash is disabled by the clearing of XPEN bit in SYSCON. 5.6.5 Watchdog As for standard boot, the Watchdog timer remains disabled during Alternate Boot Mode. In case a Watchdog reset occurs, a software reset is generated. Note: See note from Section 5.2.7 concerning software reset. 5.6.6 Exiting alternate boot mode Once the ABM mode is entered, it can be exited only with a software or hardware reset. Note: See note from Section 5.2.7 concerning software reset. 5.6.7 Alternate boot user software If the rules described previously are respected (that is, mapping of variables, disabling of interrupts, exit conditions, predefined vectors in Block 0 of Bank 2, Watchdog usage), then users can write the software they want to execute in this mode starting from 09’0000h. 5.6.8 User/alternate mode signature integrity check The behavior of the Alternate Boot Mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature. This requires that users who use Alternate Boot have reserved and programmed the Flash memory locations according to: User mode signature 00'0000h: memory address of operand0 for the signature computing 00’1FFCh: memory address of operand1 for the signature computing 00’1FFEh: memory address for the signature reference Alternate mode signature 09'0000h: memory address of operand0 for the signature computing 09’1FFCh: memory address of operand1 for the signature computing 09’1FFEh: memory address for the signature reference |
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