ST10F276E datasheet(193/235 Pages) STMICROELECTRONICS

193 / 235 page

ST10F276E

Electrical characteristics

Doc ID 12303 Rev 3

193/235

The formula above places constraints on external network design, in particular on resistive

path.

A second aspect involving the capacitance network must be considered. Assuming the three

capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the

equivalent circuit shown in Figure 47), when the sampling phase is started (A/D switch

close), a charge sharing phenomena is installed.

Figure 48.

Charge sharing timing diagram during sampling phase

In particular two different transient periods can be distinguished (see Figure 48):

A first and quick charge transfer from the internal capacitances CP1 and CP2 to the

sampling capacitance CS occurs (CS is supposed initially completely discharged):

Considering a worst case (since the time constant in reality would be faster) in which

CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and

CS are in series and the time constant is:

This relation can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been

designed to also be robust in the very worst case: The sampling time TS is always

much longer than the internal time constant:

The charge of CP1 and CP2 is also redistributed on CS, determining a new value of the

voltage VA1 on the capacitance according to the following equation:

A second charge transfer also involves CF (that is typically bigger than the on-chip

capacitance) through the resistance RL: Again considering the worst case in which CP2

and CS were in parallel to CP1 (since the time constant in reality would be faster), the

time constant is:

In this case, the time constant depends on the external circuit: In particular, imposing

()

⋅

-----------------------

⋅

()

⋅

<< TS

()

⋅

()

⋅

()

⋅

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