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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST10F276E 데이터시트(PDF) 222 Page - STMicroelectronics |
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ST10F276E 데이터시트(HTML) 222 Page - STMicroelectronics |
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222 / 235 page  Electrical characteristics ST10F276E 222/235 Doc ID 12303 Rev 3 23.8.21 External bus arbitration VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF Figure 66. External bus arbitration (releasing the bus) 1. The ST10F276E will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64. Table 107. External bus arbitration Symbol Parameter fCPU = 40 MHz TCL = 12.5ns Variable CPU Clock 1/2 TCL = 1 to 64 MHz Unit Min. Max. Min. Max. t61 SR HOLD input setup time to CLKOUT 18.5 - 18.5 - ns t62 CC CLKOUT to HLDA high or BREQ low delay - 12.5 - 12.5 t63 CC CLKOUT to HLDA low or BREQ high delay t64 CC CSx release 1 20 20 t65 CC CSx drive - 415- 415 t66 CC Other signals release 1 -20 - 20 t67 CC Other signals drive - 415- 415 |
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