ST10F280_12 datasheet(95/239 Pages) STMICROELECTRONICS

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ST10F280

Parallel ports

Doc ID 8673 Rev. 3

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Figure 26.

XBUS registers associated with the parallel ports

12.1

Introduction

12.1.1

Open drain mode

In the ST10F280 some ports provide Open Drain Control. This makes it possible to switch

the output driver of a port pin from a push/pull configuration to an open drain configuration.

In push/pull mode a port output driver has an upper and a lower transistor, thus it can

actively drive the line either to a high or a low level. In open drain mode the upper transistor

is always switched off, and the output driver can only actively drive the line to a low level.

When writing a ‘1’ to the port latch, the lower transistor is switched off and the output enters

a high-impedance state. The high level must then be provided by an external pull-up device.

With this feature, it is possible to connect several port pins together to a Wired-AND

configuration, saving external glue logic and/or additional software overhead for

enabling/disabling output signals.

This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections),

and is controlled through the respective Open Drain Control Registers ODPx. These

registers allow the individual bit-wise selection of the open drain mode for each port line. If

the respective control bit ODPx.y is ‘0’ (default after reset), the output driver is in the

push/pull mode. If ODPx.y is ‘1’, the open drain configuration is selected. Note that all ODPx

registers are located in the ESFR space.

Figure 27.

Output drivers in push/pull mode and in open drain mode

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